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MC33470 Synchronous Rectification DC/DC Converter Programmable Integrated Controller
The MC33470 is a digitally programmable switching voltage regulator, specifically designed for Microprocessor supply, Voltage Regulator Module and general purpose applications, to provide a high power regulated output voltage using a minimum of external parts. A 5-bit digital-to-analog converter defines the dc output voltage. This product has three additional features. The first is a pair of high speed comparators which monitor the output voltage and expedite the circuit response to load current changes. The second feature is a soft-start circuit which establishes a controlled response when input power is applied and when recovering from external circuit fault conditions. The third feature is two output drivers which provide synchronous rectification for optimum efficiency. This product is ideally suited for computer, consumer, and industrial equipment where accuracy, efficiency and optimum regulation performance is desirable.
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SOIC-20WB DW SUFFIX CASE 751D 1
MARKING DIAGRAM
20 MC33470DW AWLYYWWG 1
* 5-Bit Digital-to-Analog Converter Allows Digital Control of Output * * * * * * * * *
Voltage High Speed Response to Transient Load Conditions Output Enable Pin Provides On/Off Control Programmable Soft-Start Control High Current Output Drives for Synchronous Rectification Internally Trimmed Reference with Low Temperature Coefficient Programmable Overcurrent Protection Overvoltage Fault Indication Functionally Similar to the LTC1553 Pb-Free Packages are Available*
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
G2 1
2 PV CC PGND 3 20 G1 19 OUTEN 18 VID0 17 VID1 16 VID2 15 VID3 14 VID4 13 Pwrgd 12 Fault 11 OT
AGND 4 VCC 5 Sense 6 Imax 7 Ifb 8 SS 9 Compensation 10 (Top View) *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
1
August, 2006 - Rev. 4
Publication Order Number: MC33470/D
MC33470
OT 18 17 Voltage Identification 16 Code Input 15 14 VID0 VID1 VID2 VID3 VID4 7 Oscillator VCC 1.5 V 10 mA
+
11
Outen
19
VCC
5
Over Temp Digitally Programmed Reference Vref VCC
Over Current Detect 2.5 V PWM Comparator 90 mA En S R Q Q
190 mA
Imax 2 PV CC 20 G1
9 SS
Delay
8 Ifb 1 G2 3 PGND
0.96 Vref Vref 800 m 6 Sense 20 mA 13 Power Good
PWM Latch
+
1.04 Vref OTA Error Amp + 1.04 Vref R + Q 0.93 Vref 1.14 Vref Delay S
14 Fault
AGND
4
Compensation
10
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS (TC = 25C, unless otherwise noted.)
Rating Power Supply Voltage Symbol VCC Value 7.0 18 Unit V V V V
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Output Driver Supply Voltage (Operating) Imax, Ifb Inputs PV CC Vin Vin -0.3 to 18 All Other Inputs and Digital (OT, Fault, Power Good) Outputs Power Dissipation and Thermal Characteristics Maximum Power Dissipation Case 751D DW Suffix (TA = 70C) Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Operating Junction Temperature -0.3 to VCC + 0.3 PD RqJA RqJC TJ 0.60 91 60 125 W C/W C/W C C C Operating Ambient Temperature (Note 1) Storage Temperature Range TA 0 to +70 Tstg -55 to +125 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. ESD data available upon request
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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V,PV , = 12 V for typical values TA = Low to High [Notes 2, 3, 4], for PVCC CC min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristic OSCILLATOR Symbol Min Typ Max Unit
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Frequency (VCC = 4.5 to 5.5 V) fosc 210 300 390 kHz FEEDBACK AMPLIFIER Voltage Feedback Input Threshold (Note 5) VID0, VID1, VID2 and VID4 = "1" and VID3 = "0" VID4 = "1" and VID0, VID1, VID2 and VID3 = "0" Input Bias Current (VCM = 2.8 V) Vsense 1.764 2.744 3.43 - 1.8 2.8 3.5 20 1.836 2.856 3.57 - V IIB mA Transconductance (VCM = 2.8 V, VCOMP = 2.0 V) Open Loop Voltage Gain (VCOMP = 2.0 V) GM 400 - - - - - 800 67 1200AAA mmho - - - - - dB AVOL Output Line Regulation (VCC = 4.5 to 5.5 V) Output Load Regulation Output Current Source Sink Regline 7.0 5.0 mV mV mA Regload IOH IOL 120 120 PWM SECTION Duty Cycle at G1 Output Maximum Minimum % DCmax DCmin tPLH1 tPLH2 77 - - - 88 - 95 0 - - Propagation Delay Comp Input to G1 Output, TJ = 25C Comp Input to G2 Output, TJ = 25C ms 0.1 0.1 SOFT-START SECTION Charge Current (VSoft-Start = 0 V) Ichg 7.0 30 40 10 90 64 13 mA mA Discharge Current under Current Limit (Note 6) (VSoft-Start = 2.0 V, Vsense = Vout, Vimax = VCC, Vifb = 0 V) ISSIL 150 - Discharge Current under Hard Current Limit (VSoft-Start = 2.0 V, Vsense < Vout/2, Vimax = VCC, Vifb = 0 V) Hard Current Limit Hold Time ISSHIL tSSHIL mA ms 100 200 300 IMAX INPUT Sink Current (Vin max = VCC, Vifb = VCC) IOL 133 190 247 mA POWER GOOD OUTPUT Threshold For Logic "1" to "0" Transition Upper Threshold Lower Threshold Vth Vsense - 0.93 200 50 - - 1.04 0.96 400 100 10 1.07 - 600 150 - Response Time Logic "0" to "1" (Vsense changes from 0 V to VO) Logic "1" to "0" (Vsense changes from VO to 0 V) Sink Current (VOL = 0.5 V) trPG ms IOLPG mA mV Output Low Voltage (IOL = 100 mA) (Note 7) VOLPG 250 500 FAULT OUTPUT Threshold For Logic "0" to "1" Transition VthF trF 1.12 50 - 1.14 100 10 1.2 Vref ms Vsense Response Time Switches from 2.8 V to VCC Sink Current (VOL = 0.5 V) 150 - IOLF mA Maximum package power dissipation limits must be observed. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. VID1, VID3, VID4 = logic 0, and VID0, VID2 = logic 1. Vsense is provided from a low impedance voltage source or shorted to the output voltage. Under a typical soft current limit, the net soft-start discharge current will be 90 mA (ISSIL) - 10 mA (Ichg) = 80 mA. The soft-start sink to source current ratio is designed to be 9:1. 7. Sense (Pin 6) = 5.0 V, Comp (Pin 10) open, VID4, VID2, VID1, VID0 = 1.0, VID3 = 0. 2. 3. 4. 5. 6.
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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V,PV PVCC , = 12 V for typical values TA = Low to High [Notes 8, 9, 10],
CC for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.) Characteristic OVERTEMPERTURE OUTPUT Symbol Min Typ Max Unit
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Threshold For Logic "1" to "0" Transition (OUTEN Voltage Decreasing) Delay Time VthOUTEN tDOT IOLF 1.85 25 - 2.0 50 10 2.2 V 100 - ms Sink Current (VOL = 0.5 V) mA LOGIC INPUTS (VID0, VID1, VID2, VID3, VID4) Input Low State VIL - - - 0.8 - - V V Input High State VIH Rin 3.5 - Input Impedance 10 kW OUTPUT ENABLE CONTROL (OUTEN) Over-Temperature Driver Disable and Reset (OUTEN Voltage Decreasing) (Note 11) VOTDD 1.55 1.70 1.85 V OUTPUT SECTIONS (G1, G2) Source Resistance (Vsense = 2.0 V, VG = PV VCC - 1.0 V) Sink Resistance (Vsense = 0 V, VG = 1.0 V) CC Output Voltage with OUTEN Reset (Isink = 1.0 mA) Output Voltage Rise Time (CL = 10 nF, TJ = 25C) Output Voltage Fall Time (CL = 10 nF, TJ = 25C) ROH ROL VOL tr tf - - - - - 0.5 0.5 0.1 70 70 - - W V
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0.5 140 140 ns ns ns G1, G2 Non-Overlap Time (CL = 10 nF, TJ = 25C) tNOL 30AAAA210 150 TOTAL DEVICE Minimum Operating Voltage After Turn-On (PVCC Decreasing) PV CC Minimum Operating Voltage After Turn-On (VCC Decreasing) PV CC min VCC min ICC 10.8 3.0 - - - - - V V 4.25 8.0 - VCC Current (Note 12) (OUTEN and PVCC open, VID0, 1, 2, 3, 4 Floating) VCC 3.7 15 mA mA PV PVCC Current (OUTEN = 5.0 V, VID0, 1, 2, 3, 4 Open,PV PVCC = 12 V) CC CC PI CC 8. Maximum package power dissipation limits must be observed. 9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 10. VID1, VID3, VID4 = logic 0, and VID0, VID2 = logic 1. 11. OUTEN is internally pulled low if VID0, 1, 2, 3, and 4 are floating. 12. Due to internal pullup resistors, there will be an additional 0.5 mA per pin if any of the VID0, 1, 2, 3, or 4 pins are pulled low.
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MC33470
8.0 I CC, SUPPLY CURRENT (mA) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 200 nS/DIV 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 INPUT VOLTAGE (V) PV + 12 V CC PV + Open CC TA = 25C
2.0 V/DIV
VO = 2.8 V IO = 3.3 A Figure 14 Circuit
Figure 2. Output Drive Waveform
Figure 3. 5.0 V Supply Current
0 PV CC -0.5 -1.0 500 mV/DIV Source Saturation (Load to Ground)
0
VO = 2.8 V IO transient = 0.3 to 16 A Figure 14 Circuit
1.0 0.5
Sink Saturation (Load to PV ) CC Ground
0 2.5 mS/DIV
0
0.2
0.4
0.6
0.8
1.0
1.2
Figure 4. Error Amplifier Transient Response
Figure 5. Drive Output Source/Sink Saturation Voltage versus Load Current
20 VO = 2.8 V IO transient = 0.3 to 16 A Figure 14 Circuit LOOP GAIN (dB) 50 mV/DIV 15 10 5.0 0 -5.0 -10 300 VCCP = 12 V VCC = 5.0 V VO = 2.8 V IO = 3.3 A TA = 25C Gain Phase
0 30 60 90 120 150 180 300 k
2.5 mS/DIV
1.0 k
3.0 k 10 k 30 k f, FREQUENCY (Hz)
100 k
Figure 6. Feedback Circuit Load Transient Response
Figure 7. Feedback Loop Gain and Phase versus Frequency
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1000 Gain 100 VCCP = 12 V VCC = 5.0 V VO = 2.8 V R2 = 18.2 k C16 = 0 TA = 25C Figure 14 0 , EXCESS PHASE (DEGREES) THRESHOLD VOLTAGE CHANGE (%) 30 60 90 Phase 120 150 1.0 1.0 10 100 FREQUENCY (kHz) 180 1000 0.8 0.6 0.4 0.2 0 -0.2 -75 IO = 3.3 A VO = 2.8 V
GAIN (mho)
10
-50
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 8. Drive Output Source/Sink Saturation Voltage versus Load Current
Figure 9. Feedback Threshold Voltage versus Temperature
4.0 2.0 IO = 3.3 A VO = 2.8 V 0 -2.0 I sense, CURRENT CHANGE (%) I max, CURRENT CHANGE (%)
5.0 4.0 2.0 0 -2.0 -4.0 -5.0 -75 IO = 3.3 A VO = 2.8 V
-4.0 -6.0 -75
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 10. Imax Current versus Temperature
Figure 11. Vsense Current Source versus Temperature
1.0 UVLO THRESHOLD CHANGE (%) 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -75 -50 -25 0 25 50 VCC Increasing IO = 3.3 A VO = 2.8 V 75 100 125 UVLO THRESHOLD CHANGE (%) 0.5
2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -75 -50 -25 0 25 50 75 100 125 IO = 3.3 A VO = 2.8 V
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 12. VCC Undervoltage Lockout Trip Point versus Temperature
Figure 13. Oscillator Frequency versus Temperature
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OUTEN D1 UP# J1-B5 R10 10 OT 11 C3 4.7 F VCC Vref + 4.0/3.8 7 + C6 1.0 F V DRIVE 2.5 V En 2 G1 R8 4.7 R4 56 20 Ifb 8 G2 1 PGnd 3 Q3 MMSF3300R2 5, 6, 7, 8 R7 4.7 4 2, 3 1.5 V PWM Comparator S Q Vref /2 R + 64 mA 0.96 Vref Vref 800 1.04 Vref OTA Error Amp + 1.04 Vref 0.96 Vref 1.14 Vref U1 4 C17 100 pF A Gnd 10 Compensation C16 2200 pF R2 8.2 k R5 1.2 k Delay Q4 MBRD1035CT MMSF3300R2 R S Q Fault 12 R6 100 k Fault Indicate + Sense 6 20 A Power Good 13 + PWM Latch Delay R9 10 12 V J1-A4, B4 Undervoltage Lockout + C1 150 F 16 V I max R1 2.7 k C5 470 pF OUTEN 19 VCC 5 18 VID0 17 VID1 16 VID2 15 VID3 14 VID4 Digitally Programmed Reference Over Temp L2 1.5 H Input Voltage Vin = 5.0 V J1-A1, A2, A3, B1, B2
J1-B6
J1-A7
Voltage Identification J1-A8 Code Input J1-B8
J1-B7
J1-A9 Oscillator VCC 10 A SS C18 9 0.01 F Over Current 190 A Detect 90 A Q1 MMSF3300R2 5, 6, 7, 8 4 2, 3
+ C2 150 F 16 V
Figure 14. MC33470 Application Circuit
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C1, C2 - C3 - C6, C13 - C10, C11 - OSCON 16SA150M TDK C3216Y5V1C476Z TDK C3216Y5V1C106Z OSCON 4SP820M
Q2 MMSF3300R2 5, 6, 7, 8 L1 1.5 H
MC33470
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VO 0.3 to 14 A J1-A10, A12, A14, A16, A18, A20, B11, B13, B15, B17, B19 D2 C10 C11 C13 820 F 820 F 1.0 F 4.0 V 4.0 V
R3 100 k
To P J1-B9
VSS J1-A11, A13, A15 A17, A19, B10, B12 B14, B16, B18, B20
J1 - AMP 532956-7 L1, L2 - Coilraft U6904
MC33470
UVL Threshold 12 V
UVL Threshold 5.0 V
Internal Vref Timing Capacitor 2.5 V 1.5 V Compensation
G1
G2
Figure 15. Timing Diagram
OPERATING DESCRIPTION The MC33470 is a monolithic, fixed frequency power switching regulator specifically designed for dc-to-dc converter applications which provide a precise supply voltage for state of the art processors. The MC33470 operates as fixed frequency, voltage mode regulator containing all the active functions required to directly implement digitally programmable step-down synchronous rectification with a minimum number of external components.
Oscillator
The oscillator frequency is internally programmed to 300 kHz. The charge to discharge ratio is controlled to yield a 95% maximum duty cycle at the switch outputs. During the fall time of the internal sawtooth waveform, the oscillator generates an internal blanking pulse that disables the G1 output switching MOSFET. The internal sawtooth waveform has a nominal peak voltage of 2.5 V and a valley voltage of 1.5 V.
Pulse Width Modulator
combination prevents multiple output pulses during a given oscillator cycle. The sense voltage input at Pin 6 is applied to the noninverting inputs of a pair of high speed comparators. The high speed comparators' inverting inputs are tied 0.96 x Vref and 1.04 x Vref, respectively, to provide an optimum response to load changes. When load transients which cause the output voltage to fall outside a "4% regulation window occur, the high speed comparators override the PWM comparator to force a zero or maximum duty cycle operating condition until the output voltage is once again within the linear window. When voltages are initially provided to the supply pins, VCC and PV , undervoltage lockout circuits monitor each
CC
of the supply voltage levels. Both G1 and G2 output pins are held low until the VCC pin voltage exceeds 4.0 V and the pin voltage exceeds 9.0 V. PV
CC Error Amplifier and Voltage Reference
The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the noninverting input, while the error amplifier output is applied to the inverting input. Output switch conduction is initiated when the ramp waveform is discharged to the valley voltage. As the ramp voltage increases to a voltage that exceeds the error amplifier output, the latch resets, terminating output G1 MOSFET conduction, and turning on output G2 MOSFET, for the duration of the oscillator ramp. This PWM/latch
The error amplifier is a transconductance type amplifier, having a nominal transconductance of 800 mmho. The transconductance has a negative temperature coefficient. Typical transconductance is 868 mmho at 0C and 620 mmho at 125C junction temperature. The amplifier has a cascode output stage which provides a typical 3.0 Mega-Ohms of impedance. The typical error amplifier dc voltage gain is 67 dB.
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MC33470
External loop compensation is required for converter stability. Compensation components may be connected from the compensation pin to ground. The error amplifier input is tied to the sense pin which also has an internal 20 mA current source to ground. The current source is intended to provide a 24 mV offset when an external 1.2 k resistor is placed between the output voltage and the sense pin. The 24 mV offset voltage is intended to allow a greater dynamic load regulation range within a given specified tolerance for the output voltage. The offset may be increased by increasing the resistor value. The offset can be eliminated by connecting the sense pin directly to the regulated output voltage. The voltage reference consists of an internal, low temperature coefficient, reference circuit with an added offset voltage. The offset voltage level is the output of the digital-to-analog converter. Control bits VID0 through VID4 control the amount of offset voltage which sets the value of the voltage reference, as shown in Table 1. The VID0-4 input bits each have internal 10 k pullup resistances. Therefore, the reference voltage, and the output voltage, may be programmed by connecting the VID pins to ground for logic "0" or by an open for a logic "1". Typically, a logic "1" will be recognized by a voltage > 0.67 x VCC. A logic "0" is a voltage < VCC/3.
MOSFET Switch Outputs
Because the Imax pin draws 190 mA of input current, the overcurrent threshold is programmed by an external resistor. Referring to Figure 14, the current limit resistor value can be determined from the following equation:
R1 + [( I )( R )] L(max) DS(on) (Imax) I I L(max) + )I
where:
O ripple 2
IO = Maximum load current Iripple = Inductor peak to peak ripple current OUTEN Input and OT Output Pins
The output MOSFETs are designed to switch a maximum of 18 V, with a peak drain current of 2.0 A. Both G1 and G2 output drives are designed to switch N-channel MOSFETs. Output drive controls to G1 and G2 are phased to prevent cross conduction of the internal IC output stages. Output dead time is typically 100 nanoseconds between G1 and G2 in order to minimize cross conduction of the external switching MOSFETs.
Current Limit and Soft-Start Controls
On and off control of the MC33470 may be implemented with the OUTEN pin. A logic "1" applied the OUTEN pin, where a logic "1" is above 2.0 V, will allow normal operation of the MC33470. The OUTEN pin also has multiple thresholds to provide over temperature protection. An negative temperature coefficient thermistor can be connected to the OUTEN pin, as shown in Figure 16. Together with RS, a voltage divider is formed. The divider voltage will decrease as the thermistor temperature increases. Therefore, the thermistor should be mounted to the hottest part on the circuit board. When the OUTEN voltage drops below 2.0 V typically, the MC33470 OT pin open collector output will switch from a logic "1" to a logic "0", providing a warning to the system. If the OUTEN voltage drops below 1.7 V, both G1 and G2 output driver pins are latched to a logic "0" state.
VCC
10 k OT VCC
The soft-start circuit is used both for initial power application and during current limit operation. A single external capacitor and an internal 10 mA current source control the rate of voltage increase at the error amplifier output, establishing the circuit turn on time. The G1 output will increase from zero duty cycle as the voltage across the soft-start capacitor increases beyond about 0.5 V. When the soft-start capacitor voltage has reached about 1.5 V, normal duty cycle operation of G1 will be allowed. An overcurrent condition is detected by the current limit amplifier. The current limit amplifier is activated whenever the G1 output is high. The current limit amplifier compares the voltage drop across the external MOSFET driven by G1, as measured at the IFB pin, with the voltage at the Imax pin.
RS OUTEN NTC Thermistor
MC33470
Figure 16. OUTEN/OT Overtemperature Function
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APPLICATIONS INFORMATION
Design Example
Given the following requirements, design a switching dc-to-dc converter:
VCC = VCCP = VID4-0 bits = Output current = 5.0 V 12 V 10111 - Output Voltage = 2.8 V 0.3 A to 14 A
Efficiency > 80% at full load Output ripple voltage 1% of output voltage 1. Choose power MOSFETs. In order to meet the efficiency requirement, MOSFETs should be chosen which have a low value of RDS(on). However, the threshold voltage rating of the MOSFET must also be greater than 1.5 V, to prevent turn on of the synchronous rectifier MOSFETs due to dv/dt coupling through the Miller capacitance of the MOSFET drain-to-source junction. Figure 17 shows the gate voltage transient due to this effect. In this design, choose two parallel MMSF3300 MOSFETs for both the main switch and the synchronous rectifier to maximize efficiency. 2. D VO/Vin = 2.8/5.0 = 0.56 3. Inductor selection In order to maintain continuous mode operation at 10% of full load current, the minimum value of the inductor will be: Lmin = (Vin - VO)(DTs)/(2IO min) = (5 - 2.8)(0.56 x 3.3 ms)/(2 x 1.4 A) = 1.45 mH Coilcraft's U6904, or an equivalent, provides a surface mount 1.5 mH choke which is rated for for full load current. 4. Output capacitor selection Vripple D IL x ESR, where ESR is the equivalent series resistance of the output capacitance. Therefore: ESRmax = Vripple/D IL = 0.01 x 2.8 V/1.4 A = 0.02 W maximum The AVX TPS series of tantalum chip capacitors may be chosen. Or OSCON capacitors may be used if leaded parts are acceptable. In this case, the output capacitance consists of two parallel 820 mF, 4.0 V capacitors. Each capacitor has a maximum specified ESR of 0.012 W. 5. Input Filter As with all buck converters, input current is drawn in pulses. In this case, the current pulses may be 14 A peak. If a 1.5 mH choke is used, two parallel OSCON 150 mF, 16 V capacitors will provide a filter cutoff frequency of 7.5 kHz.
6. Feedback Loop Compensation The corner frequency of the output filter with L = 1.5 mH and Co = 1640 mF is 3.2 kHz. In addition, the ESR of each output capacitor creates a zero at: fz = 1/(2 C ESR) = 1/(2 x 820 mF x 0.012) = 16.2 kHz The dc gain of the PWM is: Gain = Vin/Vpp = 5/1 = 5.0. Where Vpp is the peak-to-peak sawtooth voltage across the internal timing capacitor. In order to make the feedback loop as responsive as possible to load changes, choose the unity gain frequency to be 10% of the switching frequency, or 30 kHz. Plotting the PWM gain over frequency, at a frequency of 30 kHz the gain is about -16.5 dB = 0.15. Therefore, to have a 30 kHz unity gain loop, the error amplifier gain at 30 kHz should be 1/0.15 = 6.7. Choose a design phase margin for the loop of 60. Also, choose the error amp type to be an integrator for best dc regulation performance. The phase boost needed by the error amplifier is then 60 for the desired phase margin. Then, the following calculations can be made: k = tan [Boost/2 + 45] = tan [60/2 + 45] = 3.73 Error Amp zero freq = fc/K = 30 kHz/3.73 = 8.0 kHz Error Amp pole freq = Kfc = 3.73 x 30 kHz = 112 kHz R2 = Error Amp Gain/Gm = 6.7/800 m = 8.375 k - use an 8.2 k standard value C16 = 1/(2 R2 fz) = 1/(2 x 8.2 k x 8.0 kHz) = 2426 pF - use 2200 pF C17 = 1/(2 R2 fp) = 1/(2 x 8.2 k x 112 kHz) = 173 pF - use 100 pF The complete design is shown in Figure 14. The PC board top and bottom views are shown in Figures 18 and 19.
Figure 17. Voltage Coupling Through Miller Capacitance
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PIN FUNCTION DESCRIPTION
Pin 1 Name G2 Description This is a high current dual totem pole output Gate Drive for the Lower, or rectifier, N-channel MOSFET. Its output swings from ground to PVCC. During initial power application, both G2 and G1 are held low until both VCC and PVCC have reached proper levels. This is a separate power source connection for driving N-channel MOSFETs from the G1 and G2 outputs. It may be connected to 12 V. This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This pin is the ground for the control circuitry.
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2 3 4 5 6 7 8 PV CC PGND AGND VCC This pin is the positive supply of the control IC. Sense Imax IFB This pin is used for feedback from the output of the power supply. It has a 20 mA current source to ground which can be used to provide offset in the converter output voltage. This pin sets the current limit threshold. 190 mA must be sourced into the pin. The external resistor is determined from the following equation: R = ([RDS(on)] [ILIM]/[190 mA]) This pin has two functions. First, it provides cycle-by-cycle current limiting. Second, if the current is excessive, this pin will reinitiate a soft-start cycle. If the voltage at the IFB pin drops below the voltage at the Imax pin when G1 is on, the controller will go into current limit. The current limit circuit can be disabled by floating the Imax pin and shorting the IFB pin to VCC. This is the soft-start pin. A capacitor at this pin, in conjunction with a 10 mA internal current source, sets the soft-start time. During moderate overload (current limit with VO > 50% of the set value), the soft-start capacitor will be discharged by an internal 90 mA current source in order to reduce the duty cycle of G1. During hard current limit (current limit with VO < 50% of set value), the soft-start capacitor will be discharged by a 64 mA current source. 9 SS 10 11 Comp OT This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. This is the over temperature fault pin. OT is an open drain output that will be pulled low if the OUTEN pin is less than 2.0 V. 12 Fault This pin indicates a fault condition. Fault is an open drain output that switches low if VO exceeds 115% of its set value. Once triggered, the controller will remain in this state until the power supply is recycled or the OUTEN pin is toggled. 13 Pwrgd This pin is an open drain output which indicates that VO is properly regulated. A high level on Pwrgd indicates that VO is within "4% of its set value for more than 400 ms. Pwrgd will switch low if VO is outside "4% for more than 100 ms. Voltage ID pin. This CMOS-compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pullup resistor to VCC. Voltage ID pin. This CMOS-compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pullup resistor to VCC. Voltage ID pin. This CMOS-compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pullup resistor to VCC. Voltage ID pin. This CMOS-compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pullup resistor to VCC. Voltage ID pin. This CMOS-compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pullup resistor to VCC. 14 15 16 17 18 19 VID4 VID3 VID2 VID1 VID0 OUTEN This is the on/off control pin. A CMOS-compatible logic "1" allows the controller to operate. This pin can also be used as a temperature sensor to trigger the OT pin (when OUTEN drops below 2.0 V OT pulls low). When OUTEN drops below 1.7 V for longer than 50 ms, the controller will shut down. 20 G1 This is a high current dual totem pole output Gate Drive for the Upper, or switching, N-channel MOSFET. Its output swings from ground to PVCC. During initial power application, both G2 and G1 are held low until both VCC and PVCC have reached proper levels.
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VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Table 1. Voltage Identification Code
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
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MC33470
12 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 No CPU 2.05 1.95 1.85 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 VO - - - - - - - - -
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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PIN 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1
ORDERING INFORMATION
MC33470DWR2G
MC33470DWR2
MC33470DWG
MC33470DW
Device
Operating Temperature Range
TA = 0 to +75C
Table 2. Connector Pin Function
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MC33470
Reserved
ROW A
5.0 Vin
5.0 Vin
5.0 Vin
12 Vin
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
Ishare
VID4
VID2
VID0
VSS
VSS
VSS
VSS
VSS
13 SOIC-20WB (Pb-Free) SOIC-20WB SOIC-20WB (Pb-Free) SOIC-20WB Package Reserved OUTEN ROW B 5.0 Vin 5.0 Vin 12 Vin Pwrgd VCCP VCCP VCCP VCCP VCCP VID3 VID1 UP# VSS VSS VSS VSS VSS VSS 1000 / Tape & Reel 1000 / Tape & Reel 38 Units / Rail 38 Units / Rail Shipping
MC33470
C1 R10 L2 C2
R8 L1
R9 C3 C12
C11
C10
Figure 18. PC Board Top View
R1 C5
R3
R5 D2
Q1
Q2
Q3 Q4 C6 R7 R2 C13 C16 C17 R2 R6 R4
J1
Figure 19. PC Board Bottom View
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MC33470
PACKAGE DIMENSIONS
SOIC-20WB DW SUFFIX PLASTIC PACKAGE CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC33470/D

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